An integrated circuit (IC) hardware design engineer at the UNLV Howard R. Hughes College of Engineering is analyzing electrostatic charge accumulation on a high-speed microprocessor silicon die. The microscopic planar capacitor plate occupies a rectangular footprint:
During chemical-mechanical planarization (CMP) and high-density ion implantation, dopant dispersion produces an oscillatory non-uniform surface charge density across the die:
where and are spatial coordinates on the die face.
Excess capacitive surface charge alters transistor threshold voltages and introduces parasitic RC propagation delays across the CPU clock network. To evaluate electrostatic discharge (ESD) immunity, the engineer must:
- State the double integral formulation relating total accumulated electrostatic charge to the surface charge density over region .
- Formulate the iterated integral in the strategically optimal variable order according to Fubini's Theorem, explaining why integrating with respect to first avoids non-elementary integration.
- Evaluate the total accumulated charge in nano-Coulombs () on the microchip capacitor.